1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an improvement of a word driver for driving a word line.
2. Description of the Background Art
FIG. 17 is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter referred to as a DRAM). This DRAM is formed on a semiconductor chip CH.
A memory cell array 1 includes a plurality of word lines, a plurality bit lines crossing the plurality of word lines, and a plurality of memory cells connected to crossings of these word lines and bit lines. In FIG. 17, a word line WL, a set of bit line pairs BL, /BL and a memory cell MC connected to a crossing thereof. Each memory cell MC includes a capacitor for storing data and an N channel transistor. The N channel transistor is connected between the capacitor and a bit line, having its gate connected to a word line.
An RAS buffer 2 receives an external row address strobe signal /RAS to generate an internal row address strobe signal iRAS and a timing signal RAL. A CAS buffer 3 receives an external column address strobe signal /CAS to generate an internal column address strobe signal iCAS. A WE buffer 4 receives an external write enable signal /WE to generate an internal write enable signal iWE.
A row address buffer 5 receives an external address signal ADD to generate a row address signal RA in response to the timing signal RAL. A row decoder 6 selects any one of the plurality of word lines in the memory cell array 1 in response to the row address signal RA. A word driver 7 drives the word line WL selected by the row decoder 6 to a predetermined voltage. Data is read from a plurality of memory cells connected to selected word lines WL to respective corresponding bit line pairs. Data read to each bit line pair is amplified by a sense amplifier 12.
A column address buffer 10 receives the external address signal ADD to generate a column address signal CA in response to the internal column address strobe signal iCAS. A column decoder 11 selects any one of the plurality of bit line pairs in response to the column address signal CA. Accordingly, a selected bit line pair BL, /BL is connected to an input/output line pair IO, /IO.
In a write operation, an externally applied input data Din is provided to the input/output line pair IO, /IO through an input circuit 13. In a read operation, data on the input/output line pair IO, /IO is provided outside the chip through an output circuit 14 as output data Dout.
An RXT generating circuit 8 generates a timing signal RXT in response to the internal row address strobe signal iRAS and a portion of the row address signal RA, RAn, /RAn. An RX generating circuit 9 generates a driving signal RX having a higher voltage than a power supply voltage in response to the timing signal RXT. A control circuit 15 generates various control signals for controlling each portion in response to the internal column address strobe signal iCAS, the internal write enable signal iWE and the column address signal CA.
FIG. 18 is a diagram showing a detailed configuration of the row decoder 6 and the word driver 7.
The row decoder 6 includes a plurality of decoder circuits 60 corresponding to the plurality of word lines WL. The word driver 7 includes a plurality of driver circuits 70 corresponding to the plurality of word lines WL.
Each of the decoder circuits 60 includes an NAND gate G1. A 1-bit signal RAk of the row address signal RA or an inverted signal thereof /RAk is applied to each input terminal of the NAND gate G1, where k is an integer of 1 to n.
Each of the driver circuits 70 includes an inverter G2 and N channel transistors TR1, TR2, TR3. The transistors TR1 and TR2 are referred to as a transfer transistor and a driver transistor, respectively.
A node N1 is connected to the input terminal of the inverter G2 and the gate of the transistor TR3. The input terminal of inverter G2 is connected to a node N2. The transfer transistor TR1 is connected between the node N2 and a node N3. A power supply voltage Vcc is applied to the gate of the transfer transistor TR1.
The node N3 is connected to the gate of the driver transistor TR2. The driver transistor TR2 is connected between a node NX for receiving the driving signal RX and the word line WL. The transistor TR3 is connected between the corresponding word line WL and a ground terminal for receiving a ground potential Vss. The node N1 is connected to an output terminal of the corresponding decoder circuit 60.
Operations of a driver circuit shown in FIG. 18 will now be described with reference to a timing chart in FIG. 19. A period when the external row address strobe signal /RAS is at a logic high or "H" level is referred to as a stand-by period, while a period when the external row address strove signal /RAS is at a logic low or "L" level is referred to as an active period.
When the external row address strobe signal /RAS falls to "L", the internal row address strobe signal iRAS rises to "H" as well as the timing signal RAL rises to "H", thereby causing the external address signal ADD to be applied as the row address signal RA. As a result, the row decoder 6 decodes the row address signal RA to cause an output signal (a selecting signal) of a plurality of decoder circuits 60 to fall to "L".
Accordingly, the potential of the node N1 falls to the ground potential, causing the potential of the node N2 to rise to the power supply voltage Vcc. As a result, the potential of the node N3 becomes Vcc-Vth, where Vth is the threshold voltage of the transfer transistor TR1.
The driving signal RX rises to a high voltage Vcc+.alpha. in response to rise of the timing signal RXT. As a result, the potential of the node N3 is boosted to 2Vcc+.alpha.-Vth by a self-boosting operation of the driver transistor TR2 to cause the potential of the word line WL to rise to Vcc+.alpha.. Normally, .alpha. is set to a higher voltage than the threshold voltage of a transistor of the memory cell MC.
A power supply voltage Vcc is an internal power supply voltage down-converted by an external power supply voltage or an internal voltage down converting circuit.
A semiconductor memory device operating at a low power supply voltage is being developed in recent years with devices miniaturized. As will be described hereinafter, a low power supply voltage poses a problem of a slow rising rate of a voltage of the word line.
Assume that the power supply voltage Vcc is 5 V and that the threshold voltage Vth of the transfer transistor TR1 is 1.0 V. .alpha. is also assumed to be 1.0 V. In this case, the potential of the node N3 first rises from 0 V to 4 V. When the driving signal RX is pulled up from 0 V to 6 V, the potential of the node N3 rises from 4 V to 10 V.
Next, assume that the power supply voltage Vcc is 1.5 V and the threshold voltage Vth of the transfer transistor TR1 is 0.7 V. .alpha. is also assumed to be 1.0 V. In this case, the potential of the node N3 first rises from 0 V to 0.8 V. When the driving signal RX is pulled up from 0 V to 2.5 V, the potential of the node N3 rises from 0.8 V to 3.3 V.
As described above, when the power supply voltage Vcc is 5 V, the gate voltage of the driver transistor TR2 first attains 4 V, while when the power supply voltage Vcc is 1.5 V, the gate voltage of the driver transistor TR2 first attains 0.8 V. In other words, the lower power supply voltage brings about a smaller ratio of the voltage of the node N3 to the power supply voltage, because a ratio of the threshold voltage to the power supply voltage becomes larger.
Therefore, the conductance gm of the driver transistor TR2 becomes smaller, causing a self-boosting operation of the driver transistor TR2 to be slower. As a result, there is a problem of a longer rising time Td of the voltage of the word line WL.